Solid-state imaging device, manufacturing method thereof, and camera with alternately arranged pixel combinations

ABSTRACT

A solid-state imaging device includes a semiconductor substrate; a first conductive region of the semiconductor substrate; a first conductive region on an upper surface side of the first conductive region of the semiconductor substrate; a second conductive region below the first conductive region on the upper surface side of the first conductive region of the semiconductor substrate. The solid-state imaging device further includes a photoelectric conversion region including the first conductive region located on the upper surface side of the first conductive region of the semiconductor substrate and the second conductive region and a transfer transistor transferring charges accumulated in the photoelectric conversion region to a readout region; and a pixel including the photoelectric conversion region and the transfer transistor. The first conductive region, which is included in the photoelectric conversion region, extends to the lower side of a sidewall of a gate electrode of the transfer transistor.

CROSS REFERENCES TO RELATED APPLICATIONS

The present invention is a Continuation application of application Ser.No. 12/656,695, filed on Feb. 12, 2010, which is a Divisionalapplication of application Ser. No. 12/149,049, filed on Apr. 25, 2008,now U.S. Pat. No. 7,842,987, issued on Nov. 30, 2010, and containssubject matter related to Japanese Patent Application JP 2007-142452filed in the Japanese Patent Office on May 29, 2007, the entire contentsof which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a solid-state imaging device thatconverts a signal charge photoelectrically converted by a photoelectricconversion region into an electric signal and the resulting electricsignal is then transferred by a transfer transistor, a method ofmanufacturing such an solid-state imaging device, and an imagingapparatus provided with the solid-state imaging device.

2. Description of the Related Art

FIG. 1 illustrates a schematic cross sectional diagram of a transfertransistor used in the solid-state imaging device according to therelated art. As shown in FIG. 1, the transfer transistor includes a gateelectrode 102 formed on a first conductive type, such as a p-type,semiconductor substrate 100 through an insulating film 101. In addition,a sidewall 103 is formed on the gate electrode 102.

In a photoelectric conversion region 108, for example, an n-type secondconductor-type semiconductor region 104 is formed as a photodiodeembedded in the semiconductor substrate 100. Furthermore, for example, asurface-shield region with a p-type first conductive-type semiconductorregion 105 is formed on the second conductive-type semiconductor region104. The first conductive-type semiconductor region 105 of thephotoelectric conversion region 108 is provided for preventing thegeneration of dark current due to an influence of the interface of thesemiconductor substrate 100. A second conductive-type semiconductorregion 107 having an impurity concentration higher than that of a secondconductive-type semiconductor region 104 is formed on the semiconductorsubstrate 100 in a readout region 109 to be used as a charge readoutregion. In addition, a second conductive-type semiconductor region 106having an impurity concentration lower than that of the secondconductive-type semiconductor region 104 is formed below the sidewall toobtain an LDD structure.

Such a transfer transistor accumulates photoelectrically convertedelectrons in the second conductive-type semiconductor region 104 of thephotoelectric conversion region 108. When a high voltage is applied tothe gate electrode 102, electrons accumulated in the secondconductive-type semiconductor region 104 are transferred from thephotoelectric conversion region 108 to the readout region 109.

In the transfer transistor constructed as described above, thephotoelectrically converted charges are accumulated in a portioncomparatively deep (i.e., a deep portion) in the second conductive-typesemiconductor region 104 of the photoelectric conversion region 108.Therefore, a high voltage may need to be applied to the gate electrode102 to complete the transfer of charges. However, it is difficult toprovide the gate electrode with a high voltage when pixels are furtherminiaturized.

Furthermore, the first conductive-type semiconductor region 105 maybecome a barrier to the transfer of electrons from the photoelectricconversion region 108 to the readout region 109 in the transfertransistor constructed as described above. Thus, the firstconductive-type semiconductor region 105 is not formed below thesidewall 103 except in the case of thermal diffusion in themanufacturing process. For this reason, the interface of thesemiconductor substrate 100 exists in the second conductive-typesemiconductor region 104 below the sidewall 103. Accordingly, darkcurrent occurs in the second conductive-type semiconductor region 104due to the interface of this semiconductor substrate 100, causing adefective pixel with a white spot. When the first conductive-typesemiconductor region 105 is formed below the sidewall 103, it may be atransfer barrier and a still higher voltage may need to be applied tothe gate electrode.

Japanese Unexamined Patent Application Publication No. 2006-49921 (JP2006-49921 A), for example, has proposed a technology for reducing atransfer voltage in the configuration of the transfer transistordescribed above using an epitaxial growth method that forms asurface-shield region and an elevated source drain (ESD) region on asemiconductor substrate to reduce the transfer voltage.

SUMMARY OF THE INVENTION

However, in the configuration of the transfer transistor as described inJP 2006-49921 A, a p-type semiconductor region functioning as asurface-shield region is not formed on the interface of an n-typesemiconductor region on the lower portion of the side wall of a gateelectrode on the PD side. Therefore, it is difficult to prevent darkcurrent from being generated from the interface of the n-typesemiconductor region although a transfer voltage may be lowered, causinga defective pixel with a white spot or the like.

It is desirable to provide a solid-state imaging device which is capableof reducing a transfer voltage and preventing dark current generatedfrom the interface of a semiconductor region. Further, it is desirableto provide a method of manufacturing such a solid-state imaging deviceand an imaging apparatus provided with the solid-state imaging device.

According to an embodiment of the present invention, there is provided asolid-state imaging device. The solid-state imaging device includes: asemiconductor substrate; a first conductive region of the semiconductorsubstrate; a first conductive region located on an upper surface side ofthe first conductive region of the semiconductor substrate; a secondconductive region located below the first conductive region located onthe upper surface side of the first conductive region of thesemiconductor substrate. Further, the solid-state imaging deviceincludes a photoelectric conversion region including the firstconductive region located on the upper surface side of the firstconductive region of the semiconductor substrate and the secondconductive region. Furthermore, the solid-state imaging device includesa transfer transistor transferring charges accumulated in thephotoelectric conversion region to a readout region. The firstconductive region, which is included in the photoelectric conversionregion, extends to the lower side of a sidewall of a gate electrode ofthe transfer transistor. A pixel including the photoelectric conversionregion and the transfer transistor is provided in the solid-stateimaging device.

According to another embodiment of the present invention, there isprovided an imaging apparatus including a solid-state imaging device, animaging optical unit, and a signal processing unit. The solid-stateimaging device includes an imaging region with a pixel having aphotoelectric conversion region, a transfer transistor, and a readoutregion on a semiconductor substrate. Further, the solid-state imagingdevice includes a first conductive region of the semiconductorsubstrate, a first conductive region located on an upper surface side ofthe first conductive region of the semiconductor substrate, a secondconductive region located below the first conductive region located onthe upper surface side of the first conductive region of thesemiconductor substrate. The photoelectric conversion region includesthe first conductive region located on the upper surface side of thefirst conductive region of the semiconductor substrate and the secondconductive region. The transfer transistor transfers charges accumulatedin the photoelectric conversion region to the readout region. The firstconductive region, which is included in the photoelectric conversionregion, extends to the lower side of a sidewall of a gate electrode ofthe transfer transistor. The imaging optical unit is provided forintroducing light from an imaging subject into the solid-state imagingdevice. The signal processing unit is provided for processing signals ofan image captured by the solid-state imaging device.

According to further embodiment of the present invention, there isprovided a method of manufacturing a solid-state imaging device. Themethod includes the steps of: forming a gate electrode in a firstconductive region of a semiconductor substrate on the semiconductorsubstrate through an insulating film, forming a second conductive regionon the surface of the semiconductor substrate at an end of the gateelectrode, forming a semiconductor layer on the second conductive regionby selective epitaxial growth to form a first conductive region, andforming a sidewall of the gate electrode on the first conductive regionformed by the selective epitaxial growth.

In the solid-state imaging device and the imaging apparatus according tothe embodiments of the present invention, the first conductive region ofthe photoelectric conversion region is extended on the upper surfaceside of the semiconductor substrate to the lower portion of the sidewallof the gate electrode. Therefore, the whole surface of the photoelectricconversion region can be covered with the first conductive region,thereby preventing the generation of dark current due to the presence ofthe interface of the semiconductor substrate on the photoelectricconversion region.

In addition, the photoelectric conversion region is formed on thesurface of the semiconductor substrate and the first conductive regionis formed on the semiconductor substrate. With such a structure, thephotoelectric conversion region in which charges are accumulated isformed in a shallow portion of the semiconductor substrate. Therefore, avoltage applied to the gate electrode when transferring the chargesaccumulated in the photoelectric conversion region to the readout regioncan be reduced.

In addition, according to the method of manufacturing a solid-stateimaging device in accordance with an embodiment of the presentinvention, the first conductive region is formed on the semiconductorlayer formed on the photoelectric conversion region by selectiveepitaxial growth. Thus, the generation of dark current due to thepresence of the interface of the semiconductor substrate on thephotoelectric conversion region can be prevented. In addition, thephotoelectric conversion region is formed on the surface of thesemiconductor substrate, so that charges accumulated by photoelectricconversion can be allowed to be accumulated near the surface of thesemiconductor substrate. Thus, the transfer of charges to the readoutregion can be easily carried out.

According to the embodiments of the present invention, transfer voltagecan be reduced and dark current generated from the interface of thesemiconductor substrate can be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional diagram illustrating a transfertransistor of a solid-state imaging device according to the related art.

FIG. 2 is a schematic diagram illustrating a solid-state imaging deviceaccording to an embodiment of the present invention.

FIG. 3 is a cross sectional diagram illustrating main parts of thesolid-state imaging device according to an embodiment of the presentinvention.

FIGS. 4A to 4C are cross sectional diagrams illustrating the process ofmanufacturing a solid-state imaging device according to an embodiment ofthe present invention, wherein

FIGS. 4A to 4C correspond to the steps of the process, respectively.

FIGS. 5A to 5C are cross sectional diagram illustrating the process ofmanufacturing a solid-state imaging device according to an embodiment ofthe present invention, wherein FIGS. 5A to 5C correspond to the steps ofthe process, respectively.

FIGS. 6A to 6C are cross sectional diagrams illustrating the process ofmanufacturing a solid-state imaging device according to an embodiment ofthe present invention, wherein FIGS. 6A to 6C correspond to the steps ofthe process, respectively.

FIGS. 7A and 7B are cross sectional diagrams illustrating the process ofmanufacturing a solid-state imaging device according to an embodiment ofthe present invention, wherein FIGS. 7A and 7B correspond to the stepsof the process, respectively.

FIG. 8 is a block diagram illustrating an imaging apparatus according toan embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described with reference tothe attached drawings. FIG. 2 is a schematic diagram illustrating asolid-state imaging device in accordance with an embodiment of thepresent invention. The solid-state imaging device illustrated in FIG. 2includes a pixel unit 1, a vertical driving circuit 2, a column unit 3,a horizontal driving circuit 4, a control circuit 5, a horizontal bus 6,and an output circuit 7.

The pixel unit 1 includes a number of pixels arranged in matrix. Inaddition, the pixel unit 1 includes a pixel drive line arranged everypixel row and a vertical signal line arranged every pixel column. Pixelsare driven by pixel drive lines extending in the row direction (notshown). In addition, pixel signals are analog signals and output to therespective vertical signal lines extending in the column direction (notshown).

The vertical driving circuit 2 selects a pixel drive line and then feedsa pulse for driving the pixel to the pixel drive line. Subsequently,each of the pixel drive lines is driven, so that pixels in the row canbe driven at a time.

The control circuit 5 receives an input clock and data indicating anoperation mode or the like and outputs the internal data of thesolid-state imaging device and so on. In addition, the control circuit 5supplies clocks and pulses for driving the vertical driving circuit 2,the horizontal driving circuit 4, the column unit 3, and the outputcircuit 7.

The column unit 3 includes column circuits arranged corresponding to thecolumns of pixels. The column unit 3 reads out pixel signals of therespective columns in the pixel unit 1 through the vertical signal linesof the pixel unit 1. Subsequently, the readout pixel signals aresubjected to CDS (correlated double sampling: removing a fixed patternnoise), signal amplification processing, AD conversion processing, andso on.

The horizontal driving circuit 4 selects signals retained in the columnunit 3 in order and then leads the signals to the horizontal bus 6. Theoutput circuit 7 processes signals from the horizontal bus 6 and thenoutputs the processed signals. The output circuit 7 may, for example,carry out only buffering or carry out black-level adjacent,column-variation correction, various kinds of digital-signal processing,or the like.

Next, FIG. 3 illustrates the cross sectional diagram of a transfertransistor formed in each pixel in the solid-state imaging device of thepresent embodiment illustrated in FIG. 2. As shown in FIG. 3, thedescription is carried out using, for example, one transfer transistorformed on a pixel region among pixel regions and their peripheralcircuit regions formed on a solid-state imaging device in accordancewith an embodiment of the present invention. In a sold-state imagingdevice, furthermore, two or more transistors may be formed on the pixelregion and the peripheral circuit region thereof in addition to atransfer transistor. In other words, two or three or more transistorsare formed if required.

As shown in FIG. 3, the transfer transistor has a gate electrode 12formed on a first conductive type (e.g., p-type) semiconductor substrate10 through an insulating film 11. A sidewall 13 made of silicon nitrideor the like is formed on the side face of the gate electrode 12 throughthe insulating film 11. An insulating interlayer 14 is formed on thesemiconductor substrate 10. If a first conductive-type semiconductorregion is formed in a part of the semiconductor substrate 10, thetransfer transistor and so on may be formed on the first conductive-typesemiconductor region.

The gate electrode 12 can be formed by polysilicon or a metal gate madeof an electric conductor. The electric conductor material that forms themetal gate may be Ni silicide, which is a compound made of nickel andsilicon. In addition, as a full metal gate, a tantalum-based metal or atitanium-based metal can be used depending on the purpose of NMOS, PMOS,or the like.

A decrease in gate resistance can be attained by providing a metal gateelectrode as the gate electrode 12. According to the related art, theconnection with a gate electrode may require metal wiring provided tothe upper layer of the transistor and a contact portion to the gateelectrode formed from the metal wiring. In contrast, according to theembodiments of the present invention, the gate resistance is lowered, sothat the gate electrode can be wired directly without forming thecontact portion with the upper layer wiring. Furthermore, the upperlayer wiring is eliminated to widen the interval between the metal wiresof the respective pixels, so that the pixel aperture can be widened toincrease the sensitivity of the pixel. In addition, the number of theupper wiring layers is decreased, so that the distance from an apertureportion to a signal accumulation region can be shortened. Therefore,shading of obliquely incident light, color mixture, and so on can besuppressed.

Furthermore, the insulating film 11 used may be a high-dielectric (Hi-k)film, such as a hafnium oxide (HfO₂) film, formed by atomic layerdeposition (ALD). In FIG. 3, the insulating film 11 is formed andextends between the semiconductor substrate 10 and the gate electrode 12and between the sidewall 13 and the gate electrode 12, and covers theupper part of the insulating interlayer 14.

The transfer transistor illustrated in FIG. 3 further includes aphotoelectric conversion region 20 and a readout region 30 respectivelyformed on the opposite sides of the above gate electrode 12.

The photoelectric conversion region 20 includes a signal accumulationregion 21 and a surface shied layer 25. The signal accumulation region21 is formed on the surface of the semiconductor substrate 10 and formedof, for example, an n-type second conductive-type semiconductor region.The surface shield layer 25 is formed above the semiconductor substrate10 and formed of, for example, a p-type first conductive-typesemiconductor region.

The signal accumulation region 21 formed of the second conductive-typesemiconductor region extends from the surface of the semiconductorsubstrate 10 to the inside thereof. In addition, the signal accumulationregion 21 is formed of two or more layers with different impurityconcentrations. In other words, the uppermost portion of the signalaccumulation region 21 is formed of a second conductive-typesemiconductor region 22 containing an impurity substance, such asarsenic. In addition, the portion under the second conductive-typesemiconductor region 22 is formed of a second conductive-typesemiconductor region 23 which contains an impurity, such as arsenic, andthe impurity concentration thereof is lower than that of the secondconductive-type semiconductor region 22. Furthermore, the portion underthe second conductive-type semiconductor region 23 is formed of a secondconductive-type semiconductor region 24 which contains an impurity suchas phosphorous.

As described above, the signal accumulation region 21 is formed from thesurface 10S of the semiconductor substrate 10 to the inside thereof. Inaddition, the signal accumulation region 21 is formed so that theimpurity concentration on the side of the surface 10S of thesemiconductor substrate 10 is increased and the impurity concentrationof the deep portion thereof is lowered. Thus, electrons can beaccumulated near the surface of the semiconductor substrate 10.Therefore, a voltage applied to the gate electrode, which is used forthe transfer of electrons from the signal accumulation region 21, can bereduced. Furthermore, in the above configuration, the impurity (i.e.,arsenic) of the second conductive-type semiconductor region 22 isdispersed below the gate electrode 12. Therefore, the charges can bemore easily transferred.

Note that, in the above-described photoelectric conversion region 20,the second conductive type (e.g., n-type) signal accumulation region 21and the first conductive type (e.g., p-type) surface shield layer 25 areformed on the first conductive (e.g., p-type) semiconductor substrate10. Alternatively, n-type and p-type may be reversed. In addition, theconfiguration of the signal accumulation region 21 is not limited to onedescribed above. Alternatively, the signal accumulation region 21 may beformed using only arsenic or only phosphorous as an impurity.Furthermore, the signal accumulation region 21 is formed of a pluralityof layers with different impurity concentrations. However, the number ofthe layers is not particularly limited thereto. The signal accumulationregion 21 may be formed of one or two or more layers if required.

Furthermore, in the above configuration, the signal accumulation region21 is formed such that arsenic, a substance with a small degree ofdiffusion in the thermal process, is used on the upper surface side ofthe semiconductor substrate and phosphorous, a substance with a largedegree of diffusion in the thermal process, is used in the deep portionof the semiconductor substrate. Therefore, an impurity substance with alarger mass and a small degree of diffusion, such as arsenic, is used onthe upper surface side of the semiconductor layer, so that the signalaccumulation region 21 can be prevented from excessively diffusing fromthe signal accumulation region 21 to the readout region 30.

The surface shied layer 25 is formed above the signal accumulationregion 21. The surface shield layer 25 includes a first conductive-typesemiconductor region 26 and a first conductive-type semiconductor region27. The first conductive-type semiconductor region 26 includes animpurity substance, such as boron, and the impurity concentrationthereof is higher than that of the semiconductor substrate 10. The firstconductive-type semiconductor region 27 also includes an impuritysubstance, such as boron, and the impurity concentration thereof ishigher than that of the first conductive-type semiconductor region 26.

The surface shield layer 25 can be formed by, for example, injectingboron to a region formed by selective epitaxial growth on thesemiconductor substrate. Therefore, the lower surface of the surfaceshield layer 25 is positioned slightly near the semiconductor substrate10 by the diffusion of boron, compared with the interface between thesemiconductor substrate 10 and the epitaxial growth layer. Therefore,any defect on the surface 10S of the semiconductor substrate 10 may notexist in the signal accumulation region 21 but in the surface shieldlayer 25.

Furthermore, the first conductive-type semiconductor region 26 among theregions of the surface shield layer 25 extends to the lower side of thesidewall 13 of the above-described gate electrode 12. Thus, the firstconductive-type semiconductor region 26 covers the surface of the signalaccumulation region 21 formed on the surface 10S of the semiconductorsubstrate 10. Therefore, dark current due to a defect existing on thesurface 10S of the semiconductor substrate 10 can be prevented frombeing generated from the signal accumulation region 21. Therefore, adefected pixel with a white spot or the like can be suppressed.

In the readout region 30, a drain region 31 is formed on thesemiconductor substrate 10. That is, the drain region 31 is formed of asecond conductive-type semiconductor region and provided for reading outcharges accumulated in the photoelectric conversion region. The drainregion 31 includes a second conductive-type semiconductor region 32 anda second conductive-type semiconductor region 33. The secondconductive-type semiconductor region 32 includes an impurity substance,such as, arsenic, and the impurity concentration thereof is higher thanthat of the second conductive-type semiconductor region 22. The secondconductive-type semiconductor region 33 includes an impurity substance,such as phosphorus, and the impurity concentration thereof is higherthan that of the second conductive-type semiconductor region 32.

The drain region 31 has an elevated source drain (ESD) structure inwhich, for example, arsenic or phosphorus is injected into a region byselective epitaxial growth on the semiconductor substrate 10.

In general, when an impurity region, such as a source or a drain region,is formed in the semiconductor substrate 10, any impurity substance maybe introduced into the lower side of the gate electrode. Therefore, ithas been desired to extend the length of the gate electrode. However, ifthe above-described ESD structure is employed, the drain region 31 isformed on the semiconductor substrate 10. Thus, except for the diffusionof slight impurity by heat, the second conductive-type semiconductorregion is not formed in the semiconductor substrate 10. Therefore, thesecond conductive-type semiconductor region can be prevented frominvading the lower side of the gate electrode due to thermal diffusionand a short channel effect can be reduced. As a result, the gateelectrode length can be designed short. The area of the signalaccumulation region can be enlarged as the gate electrode length isshortened. In addition, the size of the pixel can be minimized.

Next, an example of a method of manufacturing a solid-state imagingdevice in accordance with an embodiment of the present invention will bedescribed.

First, a silicon dioxide film (SiO₂) 40, a polysilicon (poly-Si) layer41, and a silicon nitride (SiN) layer 42 are stacked on a semiconductorsubstrate 10 in this order. Subsequently, a stacked body including thesilicon dioxide film 40, the polysilicon layer 41, and the siliconnitride layer 42 is subjected to a patterning process to form a dummyelectrode 43 as illustrated in FIG. 4A.

Subsequently, a silicon nitride (SiN) film 44 is formed on a dummyelectrode 43 and a semiconductor substrate 10 by a low-pressure CVDmethod. Then, for example, arsenic is injected two times into a shallowregion of the semiconductor substrate 10 on the photoelectric conversionregion 20. In addition, for example, phosphorus is injected one timeinto a deep region of the semiconductor substrate 10. Therefore, asshown in FIG. 4B, a signal accumulation region 21 having a three-layeredstructure is formed. In the order from the upper surface side, thethree-layered structure includes a second conductive-type semiconductorregion 22 with arsenic, a second conductive-type semiconductor region 23with arsenic at a concentration lower than that of the secondconductive-type semiconductor region 22, and a second conductive-typesemiconductor region 24 with phosphorus at a concentration lower thanthat of the second conductive-type semiconductor region 22.

In this way, the signal accumulation region 21 is formed from thesurface 10S of the semiconductor substrate 10. In addition, the impurityconcentration on the side of the surface 10S in the signal accumulationregion 21 of the semiconductor substrate 10 is increased and theimpurity concentration in the deep portion in the signal accumulationregion 21 of the semiconductor substrate 10 is lowered. Accordingly,electrons can be accumulated near the surface of the semiconductorsubstrate 10.

In addition, the second conductive-type semiconductor region 22, thesecond conductive-type semiconductor region 23, and the secondconductive-type semiconductor region 24 diffuse in the lateraldirection, so that these regions can migrate toward the dummy electrode43 over the position shown in FIG. 4B. Accordingly, electrons can betransferred readily from the signal accumulation region 21, and thus avoltage to be applied to the gate electrode for the transfer can bereduced. In addition, arsenic with a comparatively large mass and asmall degree of diffusion in the thermal process may be used as animpurity for the second conductive-type semiconductor region 22 formedon the upper surface side of the semiconductor substrate 10. Thus, thesignal accumulation region 21 can be prevented from diffusing more thanneeded.

Subsequently, anisotropic etching, such as reactive ion etching (RIE),is carried out on the above silicon nitride film 44. Consequently, asshown in FIG. 4C, the silicon nitride film is removed from each of thesemiconductor substrate 10 and the signal accumulation region 21. A thinsilicon nitride film 45 is formed on the sidewall of the dummy electrode43.

Next, as illustrated in FIG. 5A, after washing the surface of thesemiconductor substrate 10 with dilute fluoric acid, a semiconductorlayer made of silicon or the like is formed on both the photoelectricconversion region 20 and the readout region 30 using the selectiveepitaxial growth method.

At this time, the semiconductor layer on the side of the photoelectricconversion region 20 is selectively grown so that it can entirely coverthe surface 10S of the above-described signal accumulation region 21.Furthermore, for example, boron at a concentration higher than that ofthe semiconductor substrate 10 is injected into the semiconductor layerformed on the side of the photoelectric conversion region 20 to form afirst conductive-type semiconductor region 26. In addition, for example,arsenic at a concentration higher than that of the secondconductive-type semiconductor region 22 is injected into thesemiconductor layer formed on the side of the readout region 30 to forma second conductive-type semiconductor region 32.

In this way, the selective epitaxial growth is carried out on thesemiconductor substrate 10 before the formation of the sidewall of thegate electrode 10, thereby forming the first conductive-typesemiconductor region 26 and the second conductive-type semiconductorregion 32. Since the sidewall of the gate electrode has not been formed,the semiconductor layer formed by the selective epitaxial growth can beformed from the both ends of the dummy electrode 43 and the siliconnitride film 45. Furthermore, the first conductive-type semiconductorregion can be formed immediately above the signal accumulation region 21formed on the surface of the semiconductor substrate 10 from one end ofthe dummy electrode 43.

At this time, the first conductive-type semiconductor region 26 slightlyenters to the side of the semiconductor substrate 10 beyond theinterface between the semiconductor substrate 10 and the epitaxialgrowth layer. Therefore, defects existing on the interface of thesemiconductor substrate 10 is not present in the signal accumulationregion 21 but in the first conductive-type semiconductor region 26.Therefore, dark current generated from a defect on the interface of thesignal accumulation region 21 can be prevented by the firstconductive-type semiconductor region 26 and the generation of a defectpixel, such as a white spot, can be suppressed.

Subsequently, the silicon nitride film 45 is removed from the side faceof the dummy electrode 43 by wet etching. Then, a SiO₂ film is formed onthe whole surface and then anisotropically etched by RIE, or the like.Accordingly, as shown in FIG. 5B, a sidewall 46 is formed on the sideface of the dummy electrode 43 by a silicon oxide (SiO₂) film.

Subsequently, after the formation of the SiN film on the whole surface,anisotropic etching such as RIE or the like is carried out.Consequently, as illustrated in FIG. 5C, a sidewall 13 formed of a SiNfilm is formed on the side face of the sidewall 46 formed of a SiO₂film. The sidewall 13 made of the SiN film is thicker than the sidewall46 formed of a SiO₂ film. Furthermore, in the photoelectric conversionregion 20 and the readout region 30, the sidewall 13 formed of the SiNfilm is formed above the first conductive-type semiconductor region 26and the second conductive-type semiconductor region 32. Thus, both thefirst conductive-type semiconductor region 26 and the secondconductive-type semiconductor region 32 are formed below the sidewall ofthe gate electrode.

Next, a semiconductor layer made of silicon or the like is formed againon the photoelectric conversion region 20 and the readout region 30 bythe selective epitaxial growth method. Then, a first conductive-typesemiconductor region 27 is formed on the semiconductor layer formed onthe side of the photoelectric conversion region 20 by, for example,injecting boron or the like at a concentration higher than that of thefirst conductive-type semiconductor region 26. In addition, asecond-conductive semiconductor region 33 is formed on the semiconductorlayer formed on the side of the readout region 30 by, for example,injecting phosphorus or the like at a concentration higher than that ofthe second conductive-type semiconductor region 32.

Therefore, as illustrated in FIG. 6A, in the photoelectric conversionregion 20, a surface shield layer 25 including the first conductive-typesemiconductor regions 26 and 27 with different impurity concentrationsis formed. Further, a drain region 31 is formed on the side of thereadout region 30. The drain region 31 includes the secondconductive-type semiconductor regions 32 and 33 with different impurityconcentrations for reading out charges accumulated in the signalaccumulation region 21.

Next, as shown in FIG. 6B, for example, a high density plasma (HDP)oxide film made of SiO₂ or the like is formed on the whole surface as aninsulating interlayer 14. Subsequently, the HDP oxide film, theinsulating interlayer 14, is planarized by chemical mechanical polishing(CMP) or the like so as to be leveled with the dummy electrode 43.

Next, as illustrated in FIG. 6C, the silicon dioxide film 40, thepolysilicon layer 41, and the silicon nitride layer 42, which form thedummy electrode 43, are removed by continuous etching. Consequently, thedummy electrode 43 can be removed.

Next, as illustrated in FIG. 7A, an insulating film 11 is formed on thewhole surface. The insulating film 11 is formed of a high-dielectric(Hi-k) film, such as a hafnium oxide (HfO₂) film, formed by atomic layerdeposition (ALD) or the like. Then, an electric conductor 47 is embeddedin an electrode portion after etching the dummy electrode 43.

Subsequently, the electric conductor 47 is etched using CMP and leveledwith the insulating film 11 to planarize the electric conductor 47,thereby forming a gate electrode 12. Consequently, the transfertransistor as illustrated in FIG. 7B can be produced.

It should be noted that a method of forming the first conductive-typesemiconductor regions 26 and 27 and the second conductive-typesemiconductor regions 32 and 33 as shown in FIG. 5A may be carried outas follows instead of the above method. For example, the firstconductive-type semiconductor region 26 (or 27) and the secondconductive-type semiconductor region 32 (or 33) are respectivelysubjected to selective epitaxial growth in which the first conductivetype or second conductive type impurity substance is added in advance.

In this case, there may be no need of ion injection to each of the firstconductive-type semiconductor region 26 (or 27) and the secondconductive-type semiconductor region 32 (or 33). Furthermore, theselective epitaxial growth, which is used in the formation of the firstconductive-type semiconductor regions 26 and 27 and the secondconductive-type semiconductor regions 32 and 33, can be carried out incommon with the selective epitaxial growth of other transistors such asPMOS transistors and MNOS transistors (not shown) of the solid-stateimaging device.

Furthermore, in the above-described transfer transistor, the gateelectrode 12 formed of the metal gate may be alternatively formed of apolysilicon. In this case, the process proceeds to the step shown inFIG. 6C. Then, the dummy gate electrode made of polysilicon is used as agate electrode 12 to produce a transfer transistor.

Furthermore, the ion injection of impurity substances as illustrated inFIGS. 5A and 6A as described above can be carried out in common with theprocess of the ion injection of other PMOS transistors and NMOStransistors (not shown in the figure) of the solid-state imaging device.For example, the ion injection for forming the first conductive-typesemiconductor region, which is the surface shield layer of thephotoelectric conversion region, may be carried out in common with theion injection for forming the first conductive-type semiconductor regionof PMOS transistor. Furthermore, the ion injection for forming thesecond conductive-type drain region of the readout region may be carriedout in common with the ion injection for forming the secondconductive-type drain region of NMOS transistor.

Furthermore, the ion injection process for forming the signalaccumulation region 21 as illustrated in FIG. 4B may be carried outafter the selective epitaxial growth illustrated in FIG. 5A. Forexample, a semiconductor layer is formed by the selective epitaxialgrowth and the ion injection is then carried out in common with the ioninjection for forming the second conductive-type semiconductor region32.

It should be noted that, in addition to the above-described processes, aheat treatment process, a surface treatment process, or the like maybesuitably added. As described above, the solid-state imaging device ofthe present embodiment can be produced.

FIG. 8 shows a block diagram of an imaging apparatus to which thesolid-state imaging device formed using the above-described transfertransistor is applied. The imaging apparatus will be described withreference to FIG. 8.

An imaging apparatus 50 as illustrated in FIG. 8 is designed as a mobilephone unit, a digital still camera, a video camera, or any of otherelectronic devices having imaging functions. The imaging apparatus 50includes an imaging optical unit 51, a solid-state imaging device 52, asignal processing unit 53, and a frame memory unit 54, a display unit55, a memory unit 56, an input unit 57, and a power supply unit 58 whichare connected to the signal processing unit 53 via a transmission line59.

The imaging optical unit 51 includes various lenses, a shutter, anaperture mechanism, and so on and guides subject image light to asolid-state imaging device 52. The solid-state imaging device 52 is theabove-described solid-state imaging device according to the embodimentand photoelectrically converts subject light passing through the imagingoptical unit to be output as a signal. The signal processing unit 53includes a digital signal processor (DSP) and so on for processingdigital signals and performs the processing, such as formatting, onimage signals output from the solid-state imaging device 52, therebyconverting the signals into display data and recording data.

The frame-memory unit 54 includes a random access memory (RAM) and so onand temporarily stores image data processed by the signal processingunit 53. The display unit 55 includes a liquid crystal display and so onand displays image data processed by the signal processing unit 53. Therecording unit 56 includes a flush memory, an erasable programmable ROM(EPROM), a hard disk (HD), and so on and stores image data. The inputunit 57 includes a shutter button, various function keys, cursor keys,and so on, which enter control signals for controlling the actions ofthe imaging apparatus from the outside. The power supply unit 58supplies operation power to each unit of the imaging apparatus 50.

The generation of dark current can be prevented by providing the imagingapparatus 50 with the solid-state imaging device of the aboveembodiment. Thus, white points or the like can be suppressed on pixels,so that an imaging apparatus with few defective pixels can be obtained.

It should be noted that the configuration of the imaging apparatus 50 isnot limited to the above-described one, and various configurations maybe employed as an alternative.

The present invention is not limited to the above configurations but canbe any of various configurations without departing from the gist of thepresent invention.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

What is claimed is:
 1. A solid-state imaging device comprising: asemiconductor substrate; an epitaxial growth layer being located on thesubstrate; and a gate electrode being located in the epitaxial growthlayer.
 2. The solid-state imaging device according to the claim 1,wherein the gate electrode is a part of a transfer transistor.
 3. Thesolid-state imaging device according to the claim 1, wherein a readoutregion being formed on the side of the gate electrode located on theepitaxial growth layer.
 4. The solid-state imaging device according tothe claim 1, wherein a photoelectric conversion region being formed inthe semiconductor substrate.
 5. The solid-state imaging device accordingto the claim 1, wherein the gate electrode having sidewalls.
 6. Thesolid-state imaging device according to the claim 3, wherein the readoutregion is a drain region.
 7. The solid-state imaging device according tothe claim 4, wherein the photoelectric conversion region is a sourceregion of the transfer transistor.
 8. The solid-state imaging deviceaccording to the claim 7, wherein the source region having one or moresemiconductor regions of the transfer transistor.